Polarity phasing of strap line for higher bit packing density of plated wire

ABSTRACT

A system for connecting the strap drivers to their respective straps of a plated wire memory array which substantially reduces the effects of the fields induced by current flow through the straps on adjacent memory elements. Adjacent pairs of strap lines are connected to their respective drivers at their opposite ends. Within each pair the strap lines are connected at the same end to their respective drivers.

United States Patent 15 3,698,011 Apicella, Jr. et al. [451 Oct. 10, 1972 [54] POLARITY PHASING OF STRAP LINE [56] References Cited FOR HIGHER BIT PACKING DENSITY OF PLATED WIRE Inventors: Anthony M. Apicella, Jr., Massillon; 1 John T. Franks, Jr., Tallmadge,

both of Ohio Assignee: Goodyear Aerospace Corporation,

Akron, Ohio Filed: April 12, 1971 Appl. No.: 132,947

US. Cl. .340/174 DC, 340/174 M, 340/ 174 PW,

340/174 TF Int. Cl ..G1lc 7/02, Gl lc 11/04, G1 lc 11/14 Field of Search ..340/ 179 PW, 179 DC OTHER PUBLICATIONS Proceedings-Fall Joint Computer Conference, 1966 pg. 293- 304.

Primary Examiner-James W. Mofiitt Attorney-J. G. Pete and L. A. Germain [57] ABSTRACT A system for connecting the strap drivers to their respective straps of a plated wire memory array which substantially reduces the effects of the fields induced by current flow through the straps on adjacent memory elements. Adjacent pairs of strap lines are connected to their respective drivers at their opposite ends. Within each pair the strap lines are connected at the same end to their respective drivers.

2 Claims, 2 Drawing Figures PATENTED UB1 1 0 I972 PRIOR ART INVENTORS ANTHONY M. APICELLA, JR. JOHN T. FRANKS, JR.

ATTORNEYS The present invention relates to plated wire memory arrays and more particularly to a novel arrangement for driving the strap lines of such arrays which substantially reduces the disturbing effects which result when several strap lines are driven at the same time.

In conventional plated wire memory arrays the current flow in all of the strap lines is in the same direction. As a result, the fields surrounding the strap lines during current flow are also oriented in the same direction. When such memory arrays are used with equipment that requires parallel operation of the strap lines, such as associative memories or associative processors, it is possible for several of the strap lines to be driven simultaneously while one strap line is not driven. If the inactive line is surrounded by driven lines, it is possible that the fields associated with the driven lines may overlap in the region of the undriven line. Since, in conventional equipment, the fields are all oriented in the same direction, the overlapping fields are additive and may be of sufficient strength to either partially or totally destroy the information previously stored in the regions of the plated wires along the undriven strap line. Heretofore, this difficulty has been avoided by sufficiently separating the adjacent strap lines so that the combined fields are not strong enough to effect the previously stored data of adjacent regions. Such an arrangement, however, does not permit a highly compact memory array and requires a greater length-of plated wire for a given number of bits than would otherwise be necessary with the resultant increased noise and signal propagation time. i

It is the primary object of the present invention to provide an arrangement for driving the strap lines of a plated wire memory array which substantially reduces the effect of the fields of the straps on adjacent regions of the array.

A further object of the invention is the provision of a strap line drive arrangement of a plated wire memory array which permits a more compact array without disturbance of adjacent memory. regions.

The above and other objects of the invention which will become apparent in the following detailed description are achieved by providing a strap line drive ar- 1 rangement in which the drivers are connected to their associated strap lines in such a manner that alternate pairs of strap lines are driven in the opposite direction.

For a more complete understanding of the invention and of the objects and advantages thereof reference should be had to the following detailed description and the accompanying drawing wherein there is showna preferred embodiment of the invention.

In the drawing:

FIG. 1 is an isometric view of a plated wire memory array with the strap lines thereof being connected in accordance with the prior art; and

FIG. 2 is a view similar to that of FIG. 1 but showing the strap lines connected in accordance with the principles of the present invention.

The reference numeral 10 of FIG. 1 designates a conventional'plated wire memory array. The array 10 includes a block or slab 12 of a dielectric material which is provided with a series of parallel bores 14 each of which receives one thin plated wire 16. Current straps 18a-18 are provided in the outer surface of the block 12 with the straps being parallel to one another and extending at right angles to the plated wires 16. Each point of crossing of the wires 16 and current straps 18 comprises a bit in the memory. As is well understood by those skilled in the art, the coating of the wire 16 is a magnetizable material and information is stored at each bit on the wire with the information being represented by the orientation of the magnetic field of the coating at that region of the wire. By the passage of current through selected ones of the straps l8a-l8h and selected ones of the wires 16, the magnetic orientation of selected regions of the wire can be aligned to record data. Also, by the passage of the current through selected ones of the straps 18a-18h and the detecting of the resultant current in selected ones of the wires 16 data can be read from the memory array. Each of the straps l8a-h is provided with a strap driver 20a-20h, respectively. v

When the memory array 10 is used in an associative processor or associative memory device where parallel read and write operations are performed, it is possible for several of the straps l8q-l8h to be energized at the same time. Since all of the straps 18a-18h are connected to their respective drivers at the same ends, the current flow through all of the straps is in parallel and in the same direction. As a result, the field which is set up around each of the energized straps during current flow is also in the same direction. If one strap, for example the strap 18d is not energized while the adjacent straps are energized, the fringes of the fields induced around the adjacent straps 18c and 18:: will overlap in the region of the unenergized strap 18d. Since the fields are oriented in the same direction, their effects are additive. Thus, the resulting field in the region of the nonenergized strap 18d may be of sufficient strength to effect the magnetic orientation of the bits on the plated wires 16 in alignment with the strap 18d. This resultant field may be of sufficient strength to alter the magnetic orientation of these bits, destroying or damaging the information previously stored there.

In order to overcome this difficulty the present invention provides a novel arrangement for driving the straps and this arrangement is shown in FIG. 2. The memory array 22 may be of the same general construction of that of FIG. 1, consisting of a dielectric block 24 provided with parallel bores 26 each receiving one plated wire 28, and straps 30a-30h arranged in parallel fashion to one another and at right angles to the wires 28. Each strap has an input 32a-32h, and an output 34a-34, respectively. Drivers 36a-36h in a novel manner. The first two drivers 36a and 36b are connected to the inputs of their respective straps 30a and 30b. The next two drivers 36c and 36d are connected to the outputs of their respective straps 30c and 30d. In the same manner, the remaining drivers are connected to their associated straps. Thus, the drivers are connected so that alternate pairs of straps are driven in the opposite direction. Current flow within each strap of the pairs of straps is in the same direction, thus current flow in the straps 30a and 30b is in the direction of the arrows 38a and 38b. However, the adjacent pairs of straps are connected so that current flow is in the opposite direction. Thus, current flow in the straps 30c and 30d is opposite to that in the straps 30a and 30b as well as opposite to that of the straps 30e and 30]".

lf any one of the straps, for example, the strap 30d is not driven while the adjacent straps 30c 30c are driven, the current flow in the two adjacent straps will be in opposite directions. The fields induced are thus also in opposite directions. The overlapping fields in the region of the inactive strap 30d are therefore in opposition to one another and cancel one another in this region. The data encoded on the plated wire 28 in the region of the strap 30d is thus unafiected by the fields surrounding the current straps 30c and 30e. A 50 percent reduction of the disturbing field has been achieved'with the novel driving arrangement of the present invention.

It will be seen that the present invention permits the closer spacing of the current strap lines since it is not necessary to provide large separations between adjacent strap lines to prevent the disturbing of data in adjacent regions. This closer possible spacing of the current strap lines results in a more compact memory array. Also, this higher packing density of the bits on the plated wire achieves a larger signal/noise ratio since a shorter sense line is now used. The signal propagation time is also decreased.

It will be understood that while only the preferred embodiment of the invention has been illustrated and described in detail herein, the invention is not so limited. Reference should therefore be had to the appended claims in determining the true scope of the invention.

What is claimed is:

1. A method for driving the current strap lines to perform read and write operations in a plated wire memory array having a plurality of plated wires arranged in spaced, parallel relation in a common plane and a plurality of current strap lines extending parallel to one another and at right angles to, but spaced from, the plated wires, which is characterized in that alternate pairs of current strap lines are driven so that current flow in the strap lines is in a first direction and the remaining pairs of current strap lines are driven so that current flow in the remaining pairs of strap lines is in the opposite direction.

2. A plated wire memory array, comprising:

a plurality of plated wires arranged in spaced, parallel relation to one another in a common plane;

a plurality of current strap lines arranged in spaced, parallel relation to one another, at right angles to the plated wires, and offset from the plated wires; and

drive means for each current strap line, the drive means being connected to their respective current strap lines in such manner that the first two current strap lines are driven in a first direction, the next two current strap lines are driven in the opposite direction and successive pairs of current strap lines are driven in alternate directions.

UNITED STATES PATENT OFFIQE QERTEFWATE GE CQRREQTMN Patent No. 011 Dated October 1972 Inventor(s) Anthony M. Apicella, Jr. and John T. Franks, Jr.

It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 2., line 2, change l8a-l8" to --l8a-18h-; line 20,

change 18a-h" to l8al8h-; line 53,after IaZa-3Zh" insert -respectively-; line 54, change "34a-34to --34a-34h--; line 54,

after "36a-36h" insert -a.re provided for each of the current stra s 365" 301 respectively. The drivers 36a-36h are connected to their respective straps 30a-30h- Signed and sealed this 10th day of April 1973.

(SEAL) Attest:

ROBERT GOTTSCHALK Attesting Officer USCOMM-DC 60376-P69 r us. GOVERNMENT PRINTING OFFICE: 1965 o-3s6-334 FORM PO-105O (10-69) 

1. A method for driving the current strap lines to perform read and write operations in a plated wire memory array having a plurality of plated wires arranged in spaced, parallel relation in a common plane and a plurality of current strap lines extending parallel to one another and at right angles to, but spaced from, the plated wires, which is characterized in that alternate pairs of current strap lines are driven so that current flow in the strap lines is in a first direction and the remaining pairs of current strap lines are driven so that current flow in the remaining pairs of strap lines is in the opposite direction.
 2. A plated wire memory array, comprising: a plurality of plated wires arranged in spaced, parallel relation to one another in a common plane; a plurality of current strap lines arranged in spaced, parallel relation to one another, at right angles to the plated wires, and offset from the plated wires; and drive means for each current strap line, the drive means being connected to their respective current strap lines in such manner that the first two current strap lines are driven in a first direction, the next two current strap lines are driven in the opposite direction and successive pairs of current strap lines are driven in alternate directions. 